منابع مشابه
A cache-friendly truncated FFT
We describe a cache-friendly version of van der Hoeven’s truncated FFT and inverse truncated FFT, focusing on the case of ‘large’ coefficients, such as those arising in the Schönhage–Strassen algorithm for multiplication in Z[x]. We describe two implementations and examine their performance.
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Increasing demand for power-efficient, high-performance computing has spurred a growing number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as servers and desktops. Despite their energy efficiency, fixed-function accelerators lack programmability, especially compared with general-purpose processors. Today’s accelerators rely on software-managed scratchpad memo...
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Operating system process scheduling has been an active area of research for many years. Process scheduling decisions can have a dramatic impact on capacity and conflict misses in on-chip caches, since processes that do not share memory will compete for entries in the cache, while processes that do share memory can effectively pre-fetch blocks or warm the cache in a symbiotic fashion. In this pa...
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Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation-induced failures in cache SRAM arrays, which compromise cache reliability. In this paper, we propose Flexible Fault-Tolerant Cache (FFT-Cache) that uses a flexible d...
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This paper introduces a new, faster sorting algorithm (ARL – Adaptive Left Radix) that does in-place, non-stable sorting. Left Radix, often called MSD (Most Significant Digit) radix, is not new in itself, but the adaptive feature and the in-place sorting ability are new features. ARL does sorting with only internal moves in the array, and uses a dynamically defined radix for each pass. ALR is a...
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ژورنال
عنوان ژورنال: Theoretical Computer Science
سال: 2009
ISSN: 0304-3975
DOI: 10.1016/j.tcs.2009.03.014